1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit.
2. Description of Related Art
With the increase of memory capacity in semiconductor memory devices, an error correction circuit which can recover errors in defective memory cells is needed. Conventional error correction circuits may be divided into error correction circuits using a redundancy memory cell and error correction circuit using error check and correction (ECC).
A semiconductor memory device including an error correction circuit using a redundancy memory cell has normal memory cells and redundancy memory cells. Here, the semiconductor memory device replaces a memory cell having an error with a redundancy memory cell when writing or reading data. Usually, dynamic random access memory (DRAM) devices use such error correction circuit using the redundancy memory cell.
Meanwhile, a semiconductor memory device including an error correction circuit using ECC generates and stores redundancy data (referred to as parity data or syndrome data) as well as a data bit and thereafter determines occurrence or non-occurrence of an error using parity bits to correct the error. The error correction circuit using the ECC is usually used for read-only memory (ROM) devices and especially for flash memory devices including electrically erasable and programmable read-only memory (EEPROM) cells.
However, when errors occur beyond an error correctable range, the error correction circuit using the ECC may miscorrect errors, that is, has a miscorrection probability. For instance, in a case where a 5-bit error detection code (EDC) and 4-bit ECC are used with respect to 528-byte information data, a miscorrection probability is about P6×0.0015 where P6 is a probability of occurrence of 6 or more bit errors. Mostly, with such error correction performance, there is not problem in system operation. However, in a particular situation such as when a large number of errors occur due to sudden degradation of a semiconductor memory device or when multiple burst errors occur due to power failure, even a moderate miscorrection probability will degrade system stability. Accordingly, an approach for reducing the miscorrection probability is required.
Conventionally, in order to reduce the miscorrection probability, cyclic redundancy check (CRC) data is added and miscorrection in ECC is detected using the CRC data. FIG. 1 is a functional block diagram of a conventional encoder. Referring to FIG. 1, a conventional semiconductor memory device includes a CRC encoder 12 and an ECC encoder 14 to encode information data.
The CRC encoder 12 receives host write data (or information data) from a host. The CRC encoder 12 generates CRC data (or CRC parity data) and adds the CRC data (or CRC parity data) to the information data. The CRC parity may be 16-bit data as illustrated in FIG. 2.
The ECC encoder 14 generates ECC parity or syndrome data for ECC with respect to the information data with the CRC data, i.e., “host write data+CRC parity”. When the ECC encoder 14 is a 4-bit ECC encoder, the ECC parity may be 52-bit data. If an even parity bit or an odd parity bit is added, the ECC parity may be a 53-bit data as illustrated in FIG. 2.
FIG. 2 illustrates an example of the structure of a conventionally encoded data. Referring to FIG. 2, after being processed by the CRC encoder 12, the encoded data is “host write data+CRC parity”. After being processed by the ECC encoder 14, the encoded data is “host write data+CRC parity+ECC parity”, which is stored in the memory.
FIG. 3 is a functional block diagram of a conventional decoder. Referring to FIG. 3, a conventional semiconductor memory device includes an ECC decoder 22, a CRC decoder 24, and a selector 26. The conventional semiconductor memory device performs decoding in a reverse order to the encoding order, that is, performs CRC decoding after performing ECC decoding on data read from the memory.
The ECC decoder 22 detects an error position by performing ECC decoding with respect to the data read from the memory and corrects an error bit according to the detected error position. The CRC decoder 24 receives corrected data from the ECC decoder 22, generates CRC data in the same manner as that performed by the CRC encoder 12, compares the generated CRC data with CRC data read from the memory, and determines occurrence or non-occurrence of an error. The CRC decoder 24 outputs a pass/fail signal according to a result of the determination. The selector 26 selects either the corrected data output from the ECC decoder 22 or predetermined uncorrectable error data in response to the pass/fail signal and outputs the selected data to the host as host read data.
In the above-described conventional method combining CRC and ECC, the miscorrection probability of 5-bit EDC/4-bit ECC is reduced to P6×0.0015×2−16 where P6 is a probability of occurrence of 6 or more bit errors. This is an improvement compared to methods that do not use a CRC circuit. When the CRC circuit is added, however, it is necessary to add CRC codec (i.e., a CRC encoder plus a CRC decoder) and a control logic for controlling the CRC codec. In addition, since CRC should be performed during encoding and decoding, additional time (i.e., an additional clock cycle) is needed.
Therefore, an approach for effectively reducing the miscorrection probability of ECC methods—while minimizing additional hardware—is needed. Furthermore, circuits and methods that reduce miscorrection probability with a minimal increase of error correction time are desired.